1. Field of the Invention
The present invention pertains to electrically programmable non-volatile memories that require a programming current, for example EPROM or EEPROM memories. They pertain more especially to a safety device for the programming of these memories.
2. Description of the Prior Art
Generally, in memories of the EPROM or EEPROM type, each data storage element or memory cell comprises a floating gate MOS transistor. A floating gate MOS transistor may have two states. For an N-channel MOS transistor, in a first state, no charge is trapped at the floating gate. There may be a conduction channel between the source and the drain. The transistor is then conductive and behaves like a closed switch. In a second state, the electrons have been trapped at the floating gate. They prevent the creation of a conduction channel in the substrate between the source and the drain. In this case, the transistor is off and behaves like an open switch.
To programme a floating-gate MOS transistor of the type described above, voltages higher than the normal operating voltage should be applied at the control gate and at one of the electrodes in such a way that the floating gate 5 can absorb and keep a charge of electrons. Furthermore, to read a memory thus programmed, a specific read voltage must be applied to the control gate. This read voltage is used to ascertain that the transistor is on or off.
To make it possible to apply the voltages needed for programming or reading a memory cell consisting of a floating-gate MOS transistor, the said transistor is generally connected in the manner shown in FIG. 1. Thus, one of the main electrodes of the floating-gate MOS transistor 1, namely the source 2 in the embodiment shown, is connected to the voltage V.sub.SS, representing the earth, while the other electrode or drain 3 is connected by a bit line (not shown) and a MOS transistor forming a switch 8 to a column address decoder 7. The control gate 5 of the MOS transistor 1 is connected by means of another connection, known as a word line (not shown) to a row address decoder. The bit lines and word lines are arranged in rows and columns to determine a matrix including the memory cell formed by the floating-gate MOS transistor 1, in a way known to the specialist. In fact, the column address decoder 7 is connected to the gate of the transistor 8, which has its source connected to the drain 3 of the transistor 1, while its drain is connected to the write circuit E and to a read circuit, the latter being symbolized by the block L.
The write circuit E is made so that a voltage corresponding substantially to the write control voltage, namely the voltage V.sub.pp, is applied at the node N when the memory cell 1 has to be programmed, i.e. when it has to record a datum, corresponding, for example, to a "1". On the contrary, if the memory cell 1 does not have to be programmed, the voltage at the node N during the writing operation is floating As shown in FIG. 1, the write circuit may be formed by a load comprising a depleted MOS transistor 11 which has one of its electrodes connected to the voltage V.sub.pp constituting the write control voltage, and its other electrode connected to one of the electrodes of an enhanced MOS transistor The other electrode of the transistor 12 is connected to the node N. The two gates of the transistors 11 and 12 are connected in common to a programming control circuit consisting of a NORgate 13 powered by the voltage V.sub.pp. This NOR gate 13 receives respectively, at its two inputs, a signal D corresponding to the inverted datum to be programmed, and a signal PGM corresponding to the inverted programming signal Consequently, with the above circuit, a voltage substantially equal to the voltage V.sub.pp is obtained at the point N only if the signals D and PGM are both at zero, i.e. the write circuit is open if the datum D equals "1" and is off if the datum D equals "0" in the embodiment chosen as an example. In fact, current is consumed at the level of V.sub.pp only when the floating-gate MOS transistor 1 is programmed. Thus, by observing the variation of the write current in a memory, it is easy to ascertain whether a logic level "1" or a logic level "0" is programmed at a given address.
This is especially troublesome for memories used to receive confidential information, because it is then easy to detect the content of the said information when programming it.
An object of the present invention is to remove these disadvantages by proposing a safety device which prevents the detection of a "1" or "0" in an electrically programmable non-volatile memory requiring a programming current.